Constant efforts are undertaken to increase the productive power of chips. A particular problem occurs here with the interference occurring between the individual conductors. If the conductor density increases in the various layers of the chip, the problem of interference couplings or cross-talk between the conductors becomes more significant. These interferences arise from the voltages induced in a conductor at no load through the switching of currents in other parallel, closely associated current-carrying conductors. The unfavorably influenced conductors lie in a close range, the effective radius of which around a current-carrying conductor varies with the signal frequency, interference capacity, inductive coupling, source and terminating impedance, dielectric constants, distance to ground and power source level, length over which the conductors run in parallel and other elements. To the extent that more conductors are arranged within a volume, high frequency switching induces voltage levels, which can be erroneously recorded as data, leading to processing errors.
Since densely packed conductors, which lie parallel to one another, are subject to cross-talk, whether from the same or adjacent layers of wiring, the valid region for the radial distance between adjacent conductors for a certain acceptable signal/noise ratio has a minimal value. This distance is usually reduced, if the conductor cross-section is reduced, the distance between the conductors is increased, the length of the coupling shortened, the dielectric constants of the insulators reduced or they are sited close to layers connected to ground. Multi-layer substrates frequently limit the number of signal planes to two layers disposed vertically to one another, adjacent to a ground layer. In another arrangement the signal layers are disposed in groups of four, wherein the conductors of adjacent signal planes are vertical to one another and each group lies between a pair of ground layers. These arrangements are typical triplet structures. Triplet structures are not applicable, however, to chips, since chips do not have voltage-ground layers but only voltage-ground conductors. In addition, these triplet structures are also not applicable to chips, since the metal layers are required almost entirely for signal wiring because of the very high wiring requirements and since the chip geometry is about an order of magnitude smaller than the geometry of a substrate (chip: 1 mm; Substrate: 100 .mu.m).
The latest generation of chips should contain 7 and more layers of metal. The distances between the conductors are reduced by up to 50% compared with CMOS chips. Capacitive and inductive interference couplings between the conductors in the different layers of wiring present a serious problem for the latest generation of chips.
German Patent DE 38 80 385 discloses a circuit board with an arrangement of tightly packed electric conductors, which are arranged in a substrate. The conductors, which lie in an area of electromagnetic influence, are arranged in parallel or common substrate channels. They converge or diverge either continuously or interrupted, if they proceed along their associated canals. Circuit board structures are conventionally triplet structures, which exhibit minimal coupling. Moreover, triplet structures are not applicable on chip structures.
U.S. Pat. No. 4,782,193 discloses a wiring structure of a chip carrier. The wiring is composed of several layers of wiring, which are connected together. The adjacent layers of wiring are arranged at fixed angles to one another, rotated preferably by about 45.degree..
The above referred patent relates to the wiring structure within a chip carrier. Chip carriers are characteristically triplet structures, which display minimal coupling. Besides triplet structures cannot be utilized on chips. In addition, the zig-zag structure is not applicable in a chip because of the wiring requirements.